Like NAND gates, NOR gates are also universal gates.

CMOS transistor structures and chip deposition geometries that produce NAND logic elements x NAND x : x AND y NOT (x NAND y) x OR y (NOT x) NAND (NOT y) XOR In English, it is not always clear whether A or B means A or B or possibly both or either A or B but not both.Desired MUX GateĪ demultiplexer performs the opposite function of a multiplexer: It takes a single input and channels it to one of two possible outputs according to a selector bit that specifies which output to choose. This construction has a propagation delay four times (instead of three times) that of a single NAND gate.Ī multiplexer or a MUX gate is a three-input gate that uses one of the inputs, called the selector bit, to select one of the other two inputs, called data bits, and outputs only the selected data bit. = NANDĪlternatively, the 4-gate version of the XOR gate can be used with an inverter. This construction entails a propagation delay three times that of a single NAND gate and uses five gates. Making other gates by using NAND gates Ī NAND gate is a universal gate, meaning that any other gate can be represented as a combination of NAND gates.Īn XNOR gate is made by considering the disjunctive normal form A ⋅ B + A ¯ ⋅ B ¯, noting from de Morgan's Law that a NAND gate is an inverted-input OR gate. As the only configuration of the two inputs that results in a low output is when both are high, this circuit implements a NAND (NOT AND) logic gate. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and Vdd (voltage source), bringing the output high. If both of the A and B inputs are low, then neither of the NMOS transistors will conduct, while both of the PMOS transistors will conduct, establishing a conductive path between the output and Vdd (voltage source), bringing the output high. In CMOS logic, if both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and Vss (ground), bringing the output low.

Nand x